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? semiconductor components industries, llc, 2016 june, 2016 ? rev. 10 1 publication order number: mc74hc4060a/d mc74hc4060a 14-stage binary ripple counter with oscillator high?performance silicon?gate cmos the mc74hc4060a is identical in pinout to the standard cmos mc14060b. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with lsttl outputs. this device consists of 14 master?slave flip?flops and an oscillator with a frequency that is controlled either by a crystal or by an rc circuit connected externally. the output of each flip?flop feeds the next and the frequency at each output is half of that of the preceding one. the state of the counter advances on the negative?going edge of the osc in. the active?high reset is asynchronous and disables the oscillator to allow very low power consumption during stand?by operation. state changes of the q outputs do not occur simultaneously because of internal ripple delays. therefore, decoded output signals are subject to decoding spikes and may have to be gated with osc out 2 of the hc4060a. features ? output drive capability: 10 lsttl loads ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 2.0 to 6.0 v ? low input current: 1 a ? high noise immunity characteristic of cmos devices ? in compliance with jedec standard no. 7a requirements ? chip complexity: 390 fets or 97.5 equivalent gates ? nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable ? these devices are pb?free, halogen free/bfr free and are rohs compliant logic diagram q4 7 q5 5 q6 4 q7 6 q8 14 q9 13 q10 15 q12 1 q13 2 q14 3 osc in 11 reset 12 pin 16 = v cc pin 8 = gnd osc out 1 osc out 2 9 10 www. onsemi.com see detailed ordering and shipping information in the package dimensions section on page 4 of this data sheet. ordering information marking diagrams soic?16 d suffix case 751b tssop?16 dt suffix case 948f 1 16 hc4060ag awlyww hc40 60a alyw 1 16 a = assembly location l, wl = wafer lot y, yy = year w, ww = work week g or = pb?free package (note: microdot may be in either location) function table clock reset output state x l l h no change advance to next state all outputs are low soic?16 tssop?16 pin assignment 16?lead package (top view) 15 16 14 13 12 11 10 2 1 34567 v cc 9 8 q10 q8 q9 reset osc in osc out 1 osc out 2 q12 q13 q14 q6 q5 q7 q4 gnd
mc74hc4060a www. onsemi.com 2 maximum ratings symbol parameter value unit v cc dc supply voltage (referenced to gnd) ?0.5 to +7.0 v v in dc input voltage (referenced to gnd) ?0.5 to v cc + 0.5 v v out dc output voltage (referenced to gnd) ?0.5 to v cc + 0.5 v i in dc input current, per pin 20 ma i out dc output current, per pin 25 ma i cc dc supply current, v cc and gnd pins 50 ma p d power dissipation in still air, soic package? tssop package? 500 450 mw t stg storage temperature range ? 65 to + 150 c t l lead temperature, 1 mm from case for 10 seconds soic or tssop package 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ?derating: soic package: ?7 mw/ c from 65 to 125 c tssop package: ?6.1 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.5* 6.0 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature range, all package types ?55 +125 c t r , t f input rise/fall time v cc = 2.0 v (figure 1) v cc = 4.5 v v cc = 6.0 v 0 0 0 1000 500 400 ns functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. *the oscillator is guaranteed to function at 2.5 v minimum. however, parametrics are tested at 2.0 v by driving pin 11 with an external clock source. dc characteristics (voltages referenced to gnd) symbo l parameter condition v cc v guaranteed limit unit ?55 to 25 c 85 c 125 c v ih minimum high?level input voltage v out = 0.1v or v cc ?0.1v |i out | 20 a 2.0 3.0 4.5 6.0 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 1.50 2.10 3.15 4.20 v v il maximum low?level input voltage v out = 0.1v or v cc ? 0.1v |i out | 20 a 2.0 3.0 4.5 6.0 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 0.50 0.90 1.35 1.80 v v oh minimum high?level output voltage (q4?q10, q12?q14) v in = v ih or v il |i out | 20 a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in =v ih or v il |i out | 2.4ma |i out | 4.0ma |i out | 5.2ma 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 v ol maximum low?level output voltage (q4?q10, q12?q14) v in = v ih or v il |i out | 20 a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v ih or v il |i out | 2.4ma |i out | 4.0ma |i out | 5.2ma 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
mc74hc4060a www. onsemi.com 3 dc characteristics (voltages referenced to gnd) (continued) symbol unit guaranteed limit v cc v condition parameter symbol unit 125 c 85 c ?55 to 25 c v cc v condition parameter v oh minimum high?level output voltage (osc out 1, osc out 2) v in = v cc or gnd |i out | 20 a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in =v cc or gnd |i out | 0.7ma |i out | 1.0ma |i out | 1.3ma 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 v ol maximum low?level output voltage (osc out 1, osc out 2) v in = v cc or gnd |i out | 20 a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in =v cc or gnd |i out | 0.7ma |i out | 1.0ma |i out | 1.3ma 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 i in maximum input leakage current v in = v cc or gnd 6.0 0.1 1.0 1.0 a i cc maximum quiescent supply current (per package) v in = v cc or gnd i out = 0 a 6.0 4 40 160 a ac characteristics (c l = 50 pf, input t r = t f = 6 ns) symbo l parameter v cc v guaranteed limit unit ?55 to 25 c 85 c 125 c f max maximum clock frequency (50% duty cycle) (figures 1 and 4) 2.0 3.0 4.5 6.0 6.0 10 30 50 9.0 14 28 45 8.0 12 25 40 mhz t plh , t phl maximum propagation delay, osc in to q4* (figures 1 and 4) 2.0 3.0 4.5 6.0 300 180 60 51 375 200 75 64 450 250 90 75 ns t plh , t phl maximum propagation delay, osc in to q14* (figures 1 and 4) 2.0 3.0 4.5 6.0 500 350 250 200 750 450 275 220 1000 600 300 250 ns t phl maximum propagation delay, reset to any q (figures 2 and 4) 2.0 3.0 4.5 6.0 195 75 39 33 245 100 49 42 300 125 61 53 ns t plh , t phl maximum propagation delay, qn to qn+1 (figures 3 and 4) 2.0 3.0 4.5 6.0 75 60 15 13 95 75 19 16 125 95 24 20 ns ac characteristics (c l = 50 pf, input t r = t f = 6 ns) ? continued symbo l parameter v cc v guaranteed limit unit ?55 to 25 c 85 c 125 c t tlh , t thl maximum output transition time, any output (figures 1 and 4) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 16 110 36 22 19 ns c in maximum input capacitance 10 10 10 pf * for t a = 25 c and c l = 50 pf, typical propagation delay from clock to other q outputs may be calculated with the following equations: v cc = 2.0 v: t p = [93.7 + 59.3 (n?1)] ns v cc = 4.5 v: t p = [30.25 + 14.6 (n?1)] ns v cc = 3.0 v: t p = [61.5+ 34.4 (n?1)] ns v cc = 6.0 v: t p = [24.4 + 12 (n?1)] ns c pd power dissipation capacitance (per package)* typical @ 25 c, v cc = 5.0 v pf 35 * used to determine the no?load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc .
mc74hc4060a www. onsemi.com 4 timing requirements (input t r = t f = 6 ns) symbo l parameter v cc v guaranteed limit unit ?55 to 25 c 85 c 125 c t rec minimum recovery time, reset inactive to clock (figure 2) 2.0 3.0 4.5 6.0 100 75 20 17 125 100 25 21 150 120 30 25 ns t w minimum pulse width, clock (figure 1) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 16 110 36 23 19 ns t w minimum pulse width, reset (figure 2) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 16 110 36 23 19 ns t r , t f maximum input rise and fall times (figure 1) 2.0 3.0 4.5 6.0 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns ordering information device package shipping ? mc74hc4060adg soic?16 (pb?free) 48 units / rail mc74hc4060adr2g soic?16 (pb?free) 2500 units / reel nlv74hc4060adr2g* soic?16 (pb?free) 2500 units / reel mc74hc4060adtg tssop?16 (pb?free) 96 units / rail mc74hc4060adtr2g tssop?16 (pb?free) 2500 units / reel NLVHC4060ADTR2G* tssop?16 (pb?free) 2500 units / reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable.
mc74hc4060a www. onsemi.com 5 pin descriptions inputs osc in (pin 11) negative?edge triggering clock input. a high?to?low transition on this input advances the state of the counter. osc in may be driven by an external clock source. reset (pin 12) active?high reset. a high level applied to this input asynchronously resets the counter to its zero state (forcing all q outputs low) and disables the oscillator. outputs q4?q10, q12?q14 (pins 7, 5, 4, 6, 13, 15, 1, 2, 3) active?high outputs. each qn output divides the clock input frequency by 2 n . the user should note the q1, q2, q3 and q11 are not available as outputs. osc out 1, osc out 2 (pins 9, 10) oscillator outputs. these pins are used in conjunction with osc in and the external components to form an oscillator. when osc in is being driven with an external clock source, osc out 1 and osc out 2 must be left open circuited. with the crystal oscillator configuration in figure 6, osc out 2 must be left open circuited. switching waveforms t w t f osc in q v cc gnd 90% 50% 10% t r t w 90% 50% 10% t phl 1/f max t plh t tlh t thl reset v cc gnd t phl 50% figure 1. figure 2. q v cc gnd 50% osc in 50% t rec 50% qn v cc gnd 50% qn+1 c l * *includes all probe and jig capacitance test point device under test output figure 3. figure 4. test circuit t plh t phl
mc74hc4060a www. onsemi.com 6 figure 5. expanded logic diagram c c r osc out 2 9 q q c c r q q c c q q c c q q c c q q c c q q4 7 q5 5 q12 1 q13 2 q14 3 q6 = pin 4 q7 = pin 6 q8 = pin 14 q9 = pin 13 q10 = pin 15 v cc = pin 16 gnd = pin 8 osc out 1 10 osc in 11 reset 12 figure 6. oscillator circuit using rc configuration reset 12 osc in 11 osc out 1 10 osc out 2 9 r tc c tc r s for 2.0v v cc 6.0v 10r tc > r s > 2r tc 400hz f 400khz: f 1 2.2r tc c tc (finhz, r tc inohms, c tc infarads) the formula may vary for other frequencies. figure 7. pierce crystal oscillator circuit reset 12 osc in 11 osc out 1 10 9 osc out 2 r f c1 c2 r1
mc74hc4060a www. onsemi.com 7 table 1. crystal oscillator amplifier specifications (t a = 25 c; input = pin 11, output = pin 10) type positive reactance (pierce) input resistance, r in 60m minimum output impedance, z out (4.5v supply) 200 (see text) input capacitance, c in 5pf typical output capacitance, c out 7pf typical series capacitance, c a 5pf typical open loop voltage gain with output at full swing, 3vdc supply 4vdc supply 5vdc supply 6vdc supply 5.0 expected minimum 4.0 expected minimum 3.3 expected minimum 3.1 expected minimum pierce crystal oscillator design figure 8. equivalent crystal networks r s l s c s re xe 2 1 2 1 2 1 c o value are supplied by crystal manufacturer (parallel resonant crystal). figure 9. series equivalent crystal load figure 10. parasitic capacitances of the amplifier z load -jx co -jx c2 r -jx c -jx cs jx ls r s r load x load note: c = c1 + c in and r = r1 + r out . c o is considered as part of the load. c a and r f typically have minimal effect below 2mhz. c in c out c a values are listed in table 1.
mc74hc4060a www. onsemi.com 8 design procedures the following procedure applies for oscillators operating below 2mhz where z is a resistor r1. above 2mhz, additional impedance elements should be considered: c out and c a of the amp, feedback resistor r f , and amplifier phase shift error from 180 c. step 1: calculate the equivalent series circuit of the crystal at the frequency of oscillation. z e jx c o (r s jx l s jx c s ) jx c o r s jx l s jx c s r e jx e reactance jx e should be positive, indicating that the crystal is operating as an inductive reactance at the oscillation frequency. the maximum r s for the crystal should be used in the equation. step 2: determine , the attenuation, of the feedback network. for a closed-loop gain of 2,a = 2, = 2/a where a is the gain of the hc4060a amplifier. step 3: determine the manufacturer?s loading capacitance. for example: a manufacturer may specify an external load capacitance of 32pf at the required frequency. step 4: determine the required q of the system, and calculate r load , for example, a manufacturer specifies a crystal q of 100,000. in-circuit q is arbitrarily set at 20% below crystal q or 80,000. then r load = (2 f o l s /q) ? r s where l s and r s are crystal parameters. step 5: simultaneously solve, using a computer, x c x c2 r r e x c2 (x e x c ) ( eq 1 (with feedback phase shift = 180 ) x e x c2 x c r e x c2 r x c load ( eq 2 (where the loading capacitor is an external load, not including c o ) r load rx c o x c2 [(x c x c2 )(x c x c o ) x c (x c x c o x c2 )] x 2 c2 (x c x c o ) 2 r 2 (x c x c o x c2 ) 2 ( eq 3 here r = r out + r1. r out is amp output resistance, r1 is z. the c corresponding to x c is given by c = c1 + c in . alternately, pick a value for r1 (i.e, let r1 = r s ). solve equations 1 and 2 for c1 and c2. use equation 3 and the fact that q = 2 f o l s /(r s + r load ) to find in-circuit q. if q is not satisfactory pick another value for r1 and repeat the procedure. choosing r1 power is dissipated in the ef fective series resistance of the crystal. the drive level specified by the crystal manufacturer is the maximum stress that a crystal can withstand without damage or excessive shift in frequency. r1 limits the drive level. to verify that the maximum dc supply voltage does not overdrive the crystal, monitor the output frequency as a function of voltage at osc out 2 (pin 9). the frequency should increase very slightly as the dc supply voltage is increased. an overdriven crystal will decrease in frequency or become unstable with an increase in supply voltage. the operating supply voltage must be reduced or r1 must be increased in value if the overdriven condition exists. the user should note that the oscillator start-up time is proportional to the value of r1. selecting r f the feedback resistor, r f , typically ranges up to 20m . r f determines the gain and bandwidth of the amplifier. proper bandwidth insures oscillation at the correct frequency plus roll-off to minimize gain at undesirable frequencies, such as the first overtone. r f must be large enough so as to not af fect the phase of the feedback network in an appreciable manner. acknowledgements and recommended references the following publications were used in preparing this data sheet and are hereby acknowledged and recommended for reading: technical note tn-24, statek corp. technical note tn-7, statek corp. d. babin, ?designing crystal oscillators?, machine design, march 7, 1985. d. babin, ?guidelines for crystal oscillator design?, machine design, april 25, 1985. also recommended for reading: e. hafner, ?the piezoelectric crystal unit-definitions and method of measurement?, proc. ieee, vol. 57, no. 2, feb., 1969. d. kemper, l. rosine, ?quartz crystals for frequency control?, electro-technology, june, 1969. p. j. ottowitz, ?a guide to crystal selection?, electronic design, may, 1966.
mc74hc4060a www. onsemi.com 9 clock reset q4 1 2 4 8 16 32 64 128 256 512 1024 2048 4096 8192 16384 q5 q6 q7 q8 q9 q10 q12 q13 q14 figure 11. timing diagram
mc74hc4060a www. onsemi.com 10 package dimensions tssop?16 case 948f issue b ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. section n?n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ?t? ?v? ?w? 0.25 (0.010) 16x ref k n n 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc74hc4060a www. onsemi.com 11 package dimensions soic?16 case 751b?05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ?b? ?a? m 0.25 (0.010) b s ?t? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint* 16 89 8x *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and are trademarks of semiconductor components industries, llc dba on semiconductor or its subsidiaries i n the united states and/or other countries. on semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property . a listing of on semiconductor?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf . on semiconductor reserves the right to make changes without further notice to any products herein. on semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does o n semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. buyer is responsible for its products and applications using on semiconductor products, including compliance with all laws, reg ulations and safety requirements or standards, regardless of any support or applications information provided by on semiconductor. ?typical? parameters which may be provided in on semiconductor data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including ?typic als? must be validated for each customer application by customer?s technical experts. on semiconductor does not convey any license under its patent rights nor the right s of others. on semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any fda class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. should buyer purchase or use on semicondu ctor products for any such unintended or unauthorized application, buyer shall indemnify and hold on semiconductor and its officers, employees, subsidiaries, affiliates, and distrib utors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that on semiconductor was negligent regarding the design or manufacture of the part. on semiconductor is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 mc74hc4060a/d literature fulfillment : literature distribution center for on semiconductor 19521 e. 32nd pkwy, aurora, colorado 80011 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative

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